1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the field of the control of data processing performance, such as, for example, so as to reduce the energy consumed by a data processing system.
2. Description of the Prior Art
An important consideration in data processing systems is their energy consumption. Data processing systems which consume less energy allow longer battery life in mobile devices, tend to run cooler and more reliably, and require fewer special engineering considerations to deal with heat dissipation and the like. It is strongly desirable to reduce the energy consumption of data processing systems.
Balanced against a desire to reduce the energy consumption of data processing systems is a simultaneous desire to increase their performance level to deal with increasingly computationally intensive tasks. Such tasks often require highly intensive processing operations for short periods of time followed by relatively long idle times in which little computation is required.
In order to address the above two factors, it is known to produce data processing systems that are able to change their performance level so that high computational performance is provided in some configurations and low energy consumptions in other configurations. Known systems, such as the LongRun software produced by Transmeta, or the SpeedStep systems produced by Intel, allow a processor to be switched between such different configurations. In order to match the desired performance goals, a high computational performance configuration would be one with a relatively high operating voltage and a relatively high processor clock frequency. Conversely, a low energy consumption configuration has a relatively low operating voltage and a relatively low processor clock frequency.
As well as providing the performance and energy management capabilities described above, another important design characteristic is that hardware and software designs should be re-useable in a relatively large number of different circumstances. If computer software, such as operating system software, has to be re-written for different hardware implementations, or the hardware designs significantly modified for different hardware implementations, then this is strongly disadvantageous.
According to one aspect the present invention provides apparatus for processing data, said apparatus comprising:                a processing circuit having a power supply configuration and driven by a clock signal, said processing circuit being operable:                    (i) in a processing mode to perform data processing operations when said power supply configuration has a processing configuration and said clock signal is clocked; and            (ii) in a holding mode to hold state without performing data processing operations when said power supply has a holding configuration and said clock signal is stopped; and                        a power supply and clock signal control circuit responsive to a target rate signal indicative of a target rate of data processing operations to be performed by said processing circuit to modulate a target rate mode control signal to switch said processing circuit between said processing mode and said holding mode so as to achieve said target rate.        
The present technique provides a system which is able to support a range of performance levels by switching between a processing mode in which the processing circuit is clocked and a holding mode in which the processing circuit is not clocked. Modulating the switching between the two modes in accordance with a target rate signal indicative of a target rate of data processing system operations allows variable performance to be achieved. Furthermore, modulating between the holding mode and the processing mode allows a wide range of performance levels to be achieved whilst requiring only two modes to be designed into the hardware, validated, tested etc. The holding mode does not perform any processing since the clock has stopped and accordingly may simply be validated to the extent of showing that state is preserved in that holding mode. The holding mode may be arranged with a power supply configuration that reduces energy consumption, such as reducing the rail voltage, using body biasing, etc. The providing of multiple performance levels without the need to provide multiple levels of voltage operation which are clocked also simplifies the integration of the processing circuit with further circuits since such a variety of operating voltages do not need to be accommodated and level shifting requirements can be reduced.
Preferred embodiments of the invention are such that the processing circuit generates a busy signal which indicates whether or not it is safe to switch the processing circuit from the processing mode to the holding mode. Thus, relatively simple power supply control circuits may be utilised with the processing circuit itself being able to override their operation so that they do not cause problems due to inappropriate power supply switching at sensitive points in the processing circuit operation, e.g. during pending data transfer with other circuit elements and the like.
The latency issues associated with operating the processing circuit in a holding mode may be addressed by providing a priority signal to override the target rate mode control signal such that the processing circuit can be switched back to the processing mode independently of the target rate or prevent it from switching into the holding mode independently of the target rate.
Particular examples of priority signals are interrupt signals and hardware real-time clock signals.
The present power control mechanism is advantageously simple to implement in that the target rate mode control signal, the busy signal and any priority signal may be logically combined with, for example, a simple OR gate in order to produce a signal for switching the processing circuit between the processing mode and the holding mode. This type of control also readily scales across multiple processing circuits which it may be desired to control in a coordinated manner.
As previously mentioned, the processing mode and the holding mode have different power supply configurations. These configurations could take a variety of different forms, the tendency being for the holding mode to be one in which energy consumption is lowered. Particularly preferred embodiments are ones in which the holding configuration corresponds to the power supply having a lower potential difference than the power supply in the processing configuration.
Given that the holding mode is one in which the processing circuit is not clocked, the potential difference in that mode may be reduced to a level which is insufficient to allow such clocking, but which produces enhanced energy saving.
Since in the holding mode the processing circuit is not clocked, simple signal clamping circuits can be provided around the processing circuit for use in the holding mode. This avoids the need to provide at least some of the more complex level shifter circuits that are required when multiple domains having different operating voltages interact with one another.
It will be appreciated that the processing circuit can take a wide variety of different forms, but the invention is particularly well suited to systems in which the processing circuit is a processor core.
In preferred embodiments of the invention active high signaling is used from the processing circuit to one or more further circuits. When the processing circuit is not being clocked and is in the holding mode, then these signals can be clamped down to ground in the same way as if the processing circuit was completely powered down.
Since the technique uses a clock signal which is modulated between being used and not used, the need to provide multiple clock signals having different frequencies is reduced. The clock frequency used may be a fixed frequency which is permanently available thus avoiding delays that can be introduced by having to start-up clock generators to supply specific intermediate frequencies corresponding to different performance levels.
It will be appreciated that when switching power supply configurations, a finite amount of time is needed to move from the holding mode configuration to the processing mode configuration and it is unsafe to start clocking in the processing circuit until the power supply has the processing mode power supply configuration properly established. Accordingly, in preferred embodiments a power supply generator provides a ready signal to the clock generator to indicate that it is safe to start clocking the processing circuit.